The present invention relates to a solid-state image pickup device of the charge-coupled type used for picking up a still picture with a high precision in an interlaced/full-frame scan read mode.
A solid-state image pickup device of the charge-coupled type (referred to also as a CCD) for picking up a still picture in an interlaced/full-frame scan read mode has been proposed in commonly assigned Japanese Patent Applications Nos. Hei-2-178654, 2-178655 and 2-178656. Such an image pickup device is superior to conventional image pickup devices using a four-phase drive system in that it suffers little smearing and can provide an improved vertical resolution.
An example of a conventional image pickup device will be described with reference to FIGS. 1 and 2. As shown in FIG. 1, the image pickup device, which is formed by IC fabricating techniques, includes layers having a proper concentration of an impurity material buried in a semiconductor substrate, and electrode layers, for example, disposed on the substrate.
A light-receiving portion 1 is formed as follows: In a p-well layer (not shown) in a semiconductor substrate, a plurality of layers formed by an n.sup.+ impurity are buried in a column (Y) direction and a row (X) direction, thereby to form an n.times.m matrix array of photodiodes (denoted as P1 to Pn for each column). Layers of an n-type impurity are buried adjacent to and alongside respective linear arrays of photodiodes, which extend in the column (Y) direction. Further, transfer gate electrodes (to be described in more detail below) are layered on the n-type impurity layers. With this structure, vertical charge transfer paths L.sub.1 to L.sub.m are formed (only vertical charge transfer paths L.sub.1, L.sub.1+1, and L.sub.1+2 are shown for ease of illustration).
A drain portion 2, which is composed of an n-type impurity at a high concentration and is employed for discharging unwanted charge, is buried in the top end portion of the vertical charge transfer paths (as viewed in the drawing). A horizontal charge transfer path 3, which is employed for transferring charge in synchronism with drive signals .alpha.1 and .alpha.2 in a two- or four-phase drive mode, is formed in the bottom end portion of the vertical charge transfer paths.
In these vertical charge transfer paths, as shown, pairs of transfer gate electrodes G.sub.11, G.sub.21, G.sub.31, G.sub.41, G.sub.12, G.sub.22, G.sub.32, G.sub.42, to G.sub.1n/2, G.sub.2n/2, G.sub.3n/2, and G.sub.4n/2 are respectively provided for the photodiodes of the columns. Since in the Y or column direction the photodiodes P1 to Pn are provided for each n number of columns, the total number of transfer gate electrodes is 2.times.n.
Channel stoppers are formed in portions of the structure (shaded portions enclosed by dotted lines) except portions which serve as transfer gates denoted as Tg (only one portion being illustrated), the portions of the photodiodes, the portions of the vertical charge transfer paths, and the portions of the horizontal charge transfer paths.
The transfer gate electrodes G.sub.11, G.sub.21, G.sub.31, G.sub.41, to G.sub.1n/2, G.sub.2n/2, G.sub.3n/2, and G.sub.4n/2 transfer pixel signals in synchronism with drive signals of prescribed timing, which are supplied from a first drive circuit 4, a second drive circuit 5, and shift registers 6 and 7.
In the image pickup device, for purposes of control, the transfer gate electrodes are divided into sets, each composed of four transfer gate electrodes, with respect to the transfer gate electrode G.sub.11 located closest to the horizontal charge transfer path 3.
In the first drive circuit 4, the first set of transfer gate electrodes G.sub.11, G.sub.12, G.sub.13, G.sub.14 to G.sub.1n/2 are connected to a signal line of a timing signal .phi..sub.L1, through NMOS transistors M.sub.11, M.sub.12, M.sub.13, to M.sub.14 to M.sub.1n/2. The second set of transfer gate electrodes G.sub.21, G.sub.22, G.sub.23, G.sub.24 to G.sub.2n/2 are connected to a signal line of a timing signal .phi..sub.L2 through NMOS transistors M.sub.21, M.sub.22, M.sub.23, M.sub.24 to M.sub.2n/2. The third set of transfer gate electrodes G.sub.31, G.sub.32, G.sub.33, G.sub.34 to G.sub.3n/2 are connected to a signal line of a timing signal .phi..sub.L3 through NMOS transistors M.sub.31, M.sub.32, M.sub.33, M.sub.34 to M.sub.3n/2. The third set of transfer gate electrodes G.sub.41, G.sub.42, G.sub.43, G.sub.44 to G.sub.4n/2 are connected to a signal line of a timing signal .phi..sub.L4 through NMOS transistors M.sub.41, M.sub.42, M.sub.43, M.sub.44 to M.sub.4n/2. The output signals S.sub.L1 to S.sub.Ln/2 of the shift register 6 are applied to the gate electrodes of the quartets of NMOS transistors.
The second set of transfer gate electrodes G.sub.21, G.sub.22, G.sub.23, G.sub.24 to G.sub.2n/2 are connected to the emitters of npn transistors Q.sub.21, Q.sub.22, Q.sub.23, Q.sub.24 to Q.sub.2n/2, the bases of which are connected to a signal .phi..sub.FSA. The fourth set of transfer gate electrodes G.sub.41, G.sub.42, G.sub.43, G.sub.44 to G.sub.4n/2 are connected to the emitters of npn transistors Q.sub.41, Q.sub.42, Q.sub.43, Q.sub.44 to Q.sub.4n/2, the bases of which are connected to a signal .phi..sub.FSB. Voltage Vs is applied to the collectors of all of the npn transistors.
The second drive circuit 5 is composed of 2.times.n NMOS transistors m.sub.11, m.sub.21, m.sub.31, m.sub.41 to m.sub.1n/2, m.sub.2n/2, m.sub.3n/2, and m.sub.4n/2, which are switched in synchronism with the signals S.sub.R1, S.sub.R2, S.sub.R3 to S.sub.Rn/2 derived from the shift register 7.
These NMOS transistors are divided into sets each of a quartet of transistors with respect to the NMOS transistor m.sub.11 closest to the horizontal charge transfer path 3. Drive signals S.sub.R1, S.sub.R2, S.sub.R3 to S.sub.Rn/2, derived from the shift register 7, are sequentially applied to the gate electrodes of those sets of transistors.
Next, the operation of the CCD when it picks up a still image will be described with reference to FIG. 2. In the image pickup mode, the timing signals .phi..sub.L1 and .phi..sub.L3 are set to the "L" level and the timing signals .phi..sub.L2 and .phi..sub.L4 are set to the "M" level.
In FIG. 2, at a time point of starting the vertical blanking period T.sub.VB, the output signals S.sub.R1 to S.sub.Rn/2 of the shift register 7 are initialized to the "L" level, and the output signals S.sub.L1 to S.sub.Ln/2 of the shift register 6 are also initialized to the "L" level.
At a time point t1 during the vertical blanking period T.sub.VB, both the signals .phi..sub.FSA and .phi..sub.FSB are simultaneously set to "HH" levels, thereby to start a field shift operation. At the instant that the signals .phi..sub.FSA and .phi..sub.FSB are simultaneously set to "HH" levels, all of the npn transistors Q.sub.21, Q.sub.41 to Q.sub.2n/2, Q.sub.4n/2 become conductive. All of the pixel signals are then shifted to the transfer elements under the even-numbered transfer gate electrode pairs G.sub.21, G.sub.41, G.sub.22, G.sub.42 to G.sub.2n/2, G.sub.4n/2 in the light-receiving portion 1.
The odd-numbered transfer gate electrode pairs G.sub.11, G.sub.31, G.sub.12, G.sub.32 to G.sub.1n/2, G.sub.3n/2 are set to the "L" level by the timing signals .phi..sub.L1 and .phi..sub.L3. To avoid mixing of the adjacent pixel signals, potential barriers are generated in the vertical charge transfer paths L1 to Ln.
Since the output signals S.sub.R1 to S.sub.Rn/2 of the shift register 7 are at the "L" level at time point t1, as stated above, the NMOS transistors m.sub.11 to m.sub.4n/2 in the second drive circuit 5 are all turned off. Accordingly, the second drive circuit 5 and all of the transfer gate electrodes G.sub.11 to G.sub.4n/2 are in an off-state. The transfer gate electrodes G.sub.11 to G.sub.4n/2 are controlled by only the signal from the first drive circuit 4.
When the vertical blanking period T.sub.VB terminates, the shift register 7 applies a start signal .phi..sub.IN1 of "M" level in synchronism with shift drive signals .phi..sub.A1 and .phi..sub.B1 during a horizontal blanking period H1. At the same time, the shift register 6 applies a start signal .phi..sub.IN2 of "L" level in synchronism with shift drive signals .phi..sub.A2 and .phi..sub.B2.
Then, during a horizontal scan period T1, the horizontal charge transfer path 3 horizontally transfers unwanted charge to the outside in synchronism with the timing signal .alpha.1 and .alpha.2.
During the first half of the horizontal blanking period H2, the shift register 7 operates in synchronism with the shift signals .phi..sub.A1 and .phi..sub.B1, so that the output signal S.sub.R1 is at the "M" level and the remaining output signals S.sub.R2 to S.sub.Rn/2 are left at the "L" level. The shift register 6 operates in synchronism with the shift signals .phi..sub.A2 and .phi..sub.B2, so that the output signal S.sub.L1 is at the "L" level and the remaining output signals S.sub.L2 to S.sub.Ln/2 are left at the "H" level.
Under this condition, the timing signals .phi..sub.R1, .phi..sub.R2, .phi..sub.R3, and .phi..sub.R4 are applied to the second drive circuit 5. Only the drive signals S.sub.11, S.sub.21, S.sub.31, and S.sub.41 are applied to the first set of transfer gate electrodes G.sub.11, G.sub.21, G.sub.31, and G.sub.41 at the same timings as the respective timing signals .phi..sub.R1, .phi..sub.R2, .phi..sub.R3, and .phi..sub.R4. The pixel signals, which correspond to the first set of the transfer gate electrodes (the pixel signals of the rows or lines of diodes P1 and P2), are transferred by one line of pixel signals toward the horizontal charge transfer path 3. The pixel signals of the line of the diodes P1 alone are transferred to the horizontal charge transfer path 3.
During the horizontal scan period T2, the horizontal charge transfer path 3 performs the horizontal transfer in synchronism with timing signals .alpha.1 and .alpha.2, so that the pixel signals of the first line (of the diodes P1) are read out in a dot-sequential order.
During the first half of a horizontal blanking period H3, the shift register 7 performs its shift operation in synchronism with the shift drive signals .phi..sub.A1 and .phi..sub.B1, so that the first and second output signals S.sub.R1 and S.sub.R2 are at the "M" level, and the remaining output signals S.sub.R3 to S.sub.Rn/2 are left at the "L" level. The shift register 6 performs the shift operation in synchronism with the shift drive signals .phi..sub.A2 and .phi..sub.B2, so that the first and second output signals S.sub.L1 and S.sub.L2 are at the "L" level, and the remaining output signals S.sub.L3 to S.sub.Ln/2 are left at the "H" level.
Under this condition, the timing signals .phi..sub.R1, .phi..sub.R2, .phi..sub.R3, and .phi..sub.R4 are applied to the second drive circuit 5. Only the drive signals S.sub.11, S.sub.21, S.sub.31, S.sub.41, S.sub.12, S.sub.22, S.sub.32, and S.sub.42 are applied to the first and second sets of transfer gate electrodes G.sub.11, G.sub.21, G.sub.31, G.sub.41, G.sub.12, G.sub.22, G.sub.32, and G.sub.42 at the same timings as the timing signals .phi..sub.R1, .phi..sub.R2, .phi..sub.R3, and .phi..sub.R4. The pixel signals which correspond to the line of the diodes P2 and the second set of the transfer gate electrodes (the lines of the diodes P3 and P4) are transferred toward the horizontal charge transfer path 3. The pixel signals of only the line of the diodes P2 are transferred to the horizontal charge transfer path 3. Only the pixel signals of the line of the diodes P1 are transferred to the horizontal charge transfer path 3.
Then, during the horizontal scan period T2, the horizontal charge transfer path 3 performs the horizontal transfer in synchronism with the timing signals .alpha.1 and .alpha.2, so that the pixel signals of the first line (of the diodes P1) are read out in a dot-sequential order.
During the next horizontal scan period T3, the horizontal charge transfer path 3 performs the horizontal transfer in synchronism with the timing signals .alpha.1 and .alpha.2, so that the pixel signals of the second line (of the diodes P2) are read out in a dot-sequential order.
Thus, every horizontal blanking period, the shift register 7 performs the shift operation to successively invert the output signals S.sub.R1 to S.sub.Rn/2 from the "L" level to the "M" level. At the same time, the shift register 6 performs the shift operation every horizontal blanking period to successively invert the output signals S.sub.R1 to S.sub.Rn/2 from the "M" level to the "L" level. In this way, the drive range of the transfer gate electrodes by the timing signals .phi..sub.R1, .phi..sub.R2, .phi..sub.R3, and .phi..sub.R4 is gradually expanded. This is continued until all of the pixel signals have been read out.
In the drive system constructed as described above, the vertical charge transfer paths L1 to Lm perform the charge transfer operations in order from the pixel signals closer to the horizontal charge transfer path 3 in successive order in a "domino" fashion. Accordingly, the drive system can read pixel signals in the noninterlaced/full-frame scan read mode using a smaller number of the transfer gates than required for the conventional four-phase drive system. The smear inherent to field scanning be remarkably reduced. Further, the vertical resolution can be improved by the reduced number of transfer gate electrodes.
In the conventional CCD as described above, as shown in FIG. 3 illustrating an enlarged view of a key portion of the CCD and FIG. 4 illustrating a cross section thereof, the widths (as viewed in the charge transfer direction) of the transfer gate electrodes G.sub.11 to G.sub.4n/2 for generating the potential barriers and the transfer elements for retaining the pixel signals in the vertical charge transfer paths are designed to be substantially equal to each other. In the field shift mode, transfer elements are alternately generated under those transfer gates (the gates G.sub.21, G.sub.41, and G.sub.22 typically illustrated in FIG. 4). At the same time, a potential barrier is generated under the remaining gate electrodes (only the gates G.sub.11, G.sub.31, and G.sub.12 and G.sub.32 typically illustrated in FIG. 4). The pixel signals of all of the diodes are field shifted to the transfer elements every line of pixel signals in successive order, as mentioned above.
Thus, in the CCD, one pair of transfer gate electrodes retains and transfers one pixel signal. Accordingly, the efficiency of charge transfer is good, but the charge quantity of each pixel signal for each pixel is not large, thereby restricting the dynamic range improvement. The known four-phase drive system transfers one pixel signal using a plural number of transfer gate electrodes. Accordingly, the quantity of charge to be transferred may be increased, but this inhibits the use of a high-precision scan read, such as the noninterlaced/full-frame read. In this respect, development of a new means solving the above problems has been required.